View ADN4694E_7848961.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

3.3 v, 100 mbps, half- and full-duplex, high speed m-lvds transceivers data sheet adn4690e /adn4692e/ ADN4694E/adn4695e rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2012 analog devices, inc. all rights reserved. features multipoint lvds transceivers (low voltage differential signaling driver and receiver pairs) switching rate: 100 mbps (50 mhz) supported bus loads: 30 to 55 choice of 2 receiver types type 1 ( adn4690e / adn4692e ): hysteresis of 25 mv type 2 ( ADN4694E / adn4695e ): threshold offset of 100 mv for open-circuit and bus-idle fail-safe conforms to tia/eia-899 standard for m-lvds glitch-free power-up/power-down on m-lvds bus controlled transition times on driver output common-mode range: ?1 v to +3.4 v, allowing communication with 2 v of ground noise driver outputs high-z when disabled or powered off enhanced esd protection on bus pins 15 kv hbm (human body model), air discharge 8 kv hbm (human body model), contact discharge 10 kv iec 61000-4-2, air discharge 8 kv iec 61000-4-2, contact discharge operating temperature range: ?40c to +85c available in 8-lead ( adn4690e / ADN4694E ) and 14-lead ( adn4692e / adn4695e ) soic packages applications backplane and cable multipoint data transmission multipoint clock distribution low power, high speed alternative to shorter rs-485 links networking and wireless base station infrastructure functional block diagrams adn4690e/ ADN4694E v cc gnd ro r d re de a b di 10471-001 figure 1. adn4692e/ adn4695e v cc gnd ro r d re de di 10471-102 a b z y figure 2. general description the adn4690e / adn4692e / ADN4694E / adn4695e are multipoint, low voltage differential signaling (m-lvds) transceivers (driver and receiver pairs) that can operate at up to 100 mbps (50 mhz). slew rate control is implemented on the driver outputs. the receivers detect the bus state with a differential input of as little as 50 mv over a common-mode voltage range of ?1 v to +3.4 v. esd protection of up to 15 kv is implemented on the bus pins. the parts adhere to the tia/eia-899 standard for m-lvds and complement tia/eia-644 lvds devices with additional multipoint capabilities. the adn4690e / adn4692e are type 1 receivers with 25 mv of hysteresis, so that slow-changing signals or loss of input does not lead to output oscillations. the ADN4694E / adn4695e are type 2 receivers exhibiting an offset threshold, guaranteeing the output state when the bus is idle (bus-idle fail-safe) or the inputs are open (open-circuit fail-safe). the parts are available as half-duplex in an 8-lead soic package (the adn4690e / ADN4694E ) or as full-duplex in a 14-lead soic package (the adn4692e / adn4695e ). a selection table for the adn469xe parts is shown in table 1. table 1. adn469xe selection table part no. receiver data rate soic duplex adn4690e type 1 100 mbps 8-lead half adn4691e type 1 200 mbps 8-lead half adn4692e type 1 100 mbps 14-lead full adn4693e type 1 200 mbps 14-lead full ADN4694E type 2 100 mbps 8-lead half adn4695e type 2 100 mbps 14-lead full adn4696e type 2 200 mbps 8-lead half adn4697e type 2 200 mbps 14-lead full
adn4690e/adn4692e/ADN4694E/adn4695e data sheet rev. a | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagrams ............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 receiver input threshold test voltages .................................... 4 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 typical performance characteristics ............................................. 8 test circui ts and switching characteristics ................................ 11 driver voltage and current measurements ............................ 11 driver timing measurements .................................................. 12 receiver timing measurements ............................................... 13 theory of operation ...................................................................... 14 half - duplex/full - duplex oper ation ....................................... 14 three - state bus connection ..................................................... 14 tr ut h tables ................................................................................. 14 glitch - fr ee power - up/power - down ....................................... 15 fault conditions ......................................................................... 15 receiver input thresholds/fail - safe ........................................ 15 applications information .............................................................. 16 outline dimensions ....................................................................... 17 ordering guide .......................................................................... 17 revis ion history 3 /12 rev. 0 to rev. a added ADN4694E and adn4695e ................................. universal change to features section , general description section, and table 1 .......................................................................................... 1 added type 2 re ceiver parameters, table 2 .................................. 3 added table 4, renumbered sequentially ..................................... 5 added type 2 receiver parameters, table 5 .................................. 5 changes to table 8 ............................................................................. 7 added table 13 ................................................................................ 14 changes to receiver input thresholds/fail - safe section and figure 35 .................................................................................... 15 changes to figure 36 and figu re 37 and their captions .......... 16 changes to ordering guide ........................................................... 18 1/12 revision 0 : initial version
data sheet adn4690e/adn4692e/ADN4694E/adn4695e rev. a | page 3 of 20 specifications v cc = 3.0 v to 3.6 v; r l = 50 ; t a = t min to t max , unless otherwise noted. 1 table 2. parameter symbol min typ max unit test conditions/comments driver differential outputs differential output voltage magnitude |v od | 480 650 mv see figure 18 ?|v od | for complementary output states ?|v od | ?50 +50 mv see figure 18 common-mode output voltage (steady state) v oc(ss) 0.8 1.2 v see figure 19, figure 22 v oc(ss) for complementary output states v oc(ss) ?50 +50 mv see figure 19, figure 22 peak-to-peak v oc v oc(pp) 150 mv see figure 19, figure 22 maximum steady-state open-circuit output voltage v a(o) , v b(o) , v y(o) , or v z(o) 0 2.4 v see figure 20 voltage overshoot low to high v ph 1.2v ss v see figure 23, figure 26 high to low v pl ?0.2v ss v see figure 23, figure 26 output current short circuit |i os | 24 ma see figure 21 high impedance state, driver only i oz ?15 +10 a C1.4 v (v y or v z ) 3.8 v, other output = 1.2 v power off i o(off) ?10 +10 a C1.4 v (v y or v z ) 3.8 v, other output = 1.2 v, 0 v v cc 1.5 v output capacitance c y or c z 3 pf v i = 0.4 sin(30e 6 t) v + 0.5 v, 2 other output = 1.2 v, de = 0 v differential output capacitance c yz 2.5 pf v ab = 0.4 sin(30e 6 t) v, 2 de = 0 v output capacitance balance (c y /c z ) c y/z 0.99 1.01 logic inputs (di, de) input high voltage v ih 2 v cc v input low voltage v il gnd 0.8 v input high current i ih 0 10 a v ih = 2 v to v cc input low current i il 0 10 a v il = gnd to 0.8 v receiver differential inputs differential input threshold voltage type 1 receiver ( adn4690e , adn4692e ) v th ?50 +50 mv see table 3, figure 35 type 2 receiver ( ADN4694E , adn4695e ) v th 50 150 mv see table 4, figure 35 input hysteresis type 1 receiver ( adn4690e , adn4692e ) v hys 25 mv type 2 receiver ( ADN4694E , adn4695e ) v hys 0 mv differential input voltage magnitude |v id | 0.05 v cc v input capacitance c a or c b 3 pf v i = 0.4 sin(30e 6 t) v + 0.5 v, 2 other input = 1.2 v differential input capacitance c ab 2.5 pf v ab = 0.4 sin(30e 6 t) v 2 input capacitance balance (c a /c b ) c a/b 0.99 1.01 logic output ro output high voltage v oh 2.4 v i oh = C8 ma output low voltage v ol 0.4 v i ol = 8 ma high impedance output current i oz ?10 +15 a v o = 0 v or 3.6 v logic input re input high voltage v ih 2 v cc v input low voltage v il gnd 0.8 v input high current i ih ?10 0 a v ih = 2 v to v cc input low current i il ?10 0 a v il = gnd to 0.8 v
adn4690e/adn4692e/ADN4694E/adn4695e data sheet rev. a | page 4 of 20 parameter symbol min typ max unit test conditions/ comments bus input/output input current a (receiver or transceiver with driver disabled) i a 0 32 a v b = 1.2 v , v a = 3.8 v ? 20 + 20 a v b = 1. 2 v , v a = 0 v or 2.4 v ? 32 0 a v b = 1.2 v , v a = ? 1.4 v b (receiver or transceiver with driver disabled) i b 0 32 a v a = 1.2 v, v b = 3.8 v ? 20 + 20 a v a = 1.2 v, v b = 0 v or 2.4 v ? 32 0 a v a = 1.2 v, v b = ? 1.4 v differential (receiver or tr ansceiver with driver disabled) i ab ? 4 + 4 a v a = v b , 1.4 v a 3.8 v power - off input current 0 v v cc 1.5 v a (receiver or transceiver) i a(off) 0 32 a v b = 1.2 v, v a = 3.8 v ? 20 + 20 a v b = 1.2 v, v a = 0 v or 2.4 v ? 32 0 a v b = 1.2 v, v a = ?1.4 v b (receiver or transceiver) i b(off) 0 32 a v a = 1.2 v, v b = 3.8 v ? 20 + 20 a v a = 1.2 v, v b = 0 v or 2.4 v ? 32 0 a v a = 1.2 v, v b = ?1.4 v differential (receiver or transceiver) i ab(off) ? 4 + 4 a v a = v b , 1.4 v v a 3.8 v in put capacitance (transceiver with driver disabled) c a or c b 5 pf v i = 0.4 sin (30 e 6 t) v + 0.5 v ,2 o ther input = 1.2 v, de = 0 v differential input capacitance (transceiver with driver disabled) c ab 3 pf v ab = 0.4 sin (30 e 6 t) v , 2 de = 0 v input capacitance balance (c a /c b ) (transceiver with driver disabled) c a / b 0.99 1.01 de = 0 v power supply supply current i cc only driver enabled 13 22 ma de, re = v cc , r l = 50 ? both driver and receiver disabled 1 4 ma de = 0 v, re = v cc , r l = no l oad both driver and receiver enabled 16 24 ma de = v cc , re = 0 v, r l = 50 ? only receiver enabled 4 13 ma de, re = 0 v, r l = 50 ? total power dissipation p d 94 mw r l = 50 ? , input (di) = 50 mhz, 50% duty cycle square wave; de = v cc ; re = 0 v ; t a = 85 c 1 all typical values are given for v cc = 3.3 v and t a = 25c. 2 hp4194a impedance analyzer (or equivalent). receiver input thres hold test voltages re = 0 v, h = high, l = l ow . table 3. test voltages for type 1 receiver applied voltages input voltage, differential input voltage, common mode receiver output v a (v) v b (v) v id (v) v ic (v) ro 2.4 0 2.4 1.2 h 0 2.4 ? 2.4 1.2 l 3.425 3.375 0.05 3.4 h 3.375 3.425 ? 0.05 3.4 l ? 0.975 ? 1.025 0.05 ? 1 h ? 1.025 ? 0.975 ? 0.05 ? 1 l
data sheet adn4690e/adn4692e/ADN4694E/adn4695e rev. a | page 5 of 20 table 4. test voltages for type 2 receiver applied voltages input voltage, differential input voltage, common mode receiver output v a (v) v b (v) v id (v) v ic (v) ro 2.4 0 2.4 1.2 h 0 2.4 ? 2.4 1.2 l 3.475 3.325 0.15 3.4 h 3.425 3.375 0.05 3.4 l ? 0.925 ? 1.075 0.15 ? 1 h ? 0.975 ? 1.025 0.05 ? 1 l timing specification s v cc = 3.0 v to 3.6 v; t a = t min to t max , unless otherwise noted. 1 table 5. parameter symbol min typ max unit test conditions/ comments driver maximum data rate 100 mbps propagation delay t plh , t phl 2 2.5 3.5 ns see figure 23, figure 26 diffe rential output rise/fall time t r , t f 2 2.6 3.2 ns see figure 23, figure 26 pulse skew |t phl ? t plh | t sk 30 150 ps see figure 23, figure 26 part -to - part skew t sk(pp) 0.9 ns see figure 23, figure 26 period jitter, rms ( one standard deviatio n ) 2 t j(per) 2 3 ps 50 mhz clock input 3 ( see figure 25 ) peak -to - peak jitter 2 , 4 t j(pp) 150 ps 100 mbps 2 15 ? 1 prbs input 5 ( see figure 28) disable time from high level t phz 4 7 ns see figure 24, figure 27 disable time from low level t plz 4 7 ns see figure 24, figure 27 enable time to high level t pzh 4 7 ns see figure 24 , figure 27 enable time to low level t pzl 4 7 ns see figure 24, figure 27 receiver propagation delay t rp lh , t rp hl 2 6 ns c l = 15 pf ( s e e figure 29 , figure 32 ) rise/fall time t r , t f 1 2.3 ns c l = 15 pf ( s ee figure 29, figure 32) pulse skew |t rp hl C t rp lh | c l = 15 pf ( see figure 29, figure 32) type 1 receiver ( adn4690e , adn4692e ) t sk 100 300 ps type 2 receiver ( ADN4694E , adn4695e ) t sk 300 500 ps part -to - part skew 6 t sk(pp) 1 ns c l = 15 pf ( s ee figu re 29, figure 32) period jitter, rms ( one standard deviation ) 2 t j(per) 4 7 ps 50 mhz clock input 3 ( see figure 31 ) peak -to - peak jitter 2 , 4 100 mbps 2 15 ? 1 prbs input 5 ( see figure 34) type 1 receiver ( adn4690e , adn4692e ) t j(pp) 200 700 ps type 2 receiver ( ADN4694E , adn4695e ) t j(p p ) 225 800 ps disable time from high level t rphz 6 10 ns see figure 30, figure 33 disable time from low level t rplz 6 10 ns see figure 30, figure 33 enable time to high level t rpzh 10 15 ns see figure 30, figure 33 enable time to low level t rpzl 10 15 ns see figure 30, figure 33 1 all typical values are given for v cc = 3.3 v and t a = 25c. 2 jitter parameters are guaranteed by design and characterization. values d o not include stimulus jitter. 3 t r = t f = 0.5 ns (10% to 90%), measured over 30,000 samples. 4 peak - to - peak jitter specifications include jitter due to pulse skew (t sk ). 5 t r = t f = 0.5 ns ( 10% to 90%), measured over 100,000 samples. 6 hp4194a impedance a nalyzer or equivalent.
adn4690e/adn4692e/ADN4694E/adn4695e data sheet rev. a | page 6 of 20 absolute maximum rat ings t a = t min to t max , unless otherwise noted. table 6. parameter rating v cc C 0.5 v to + 4 v digital input voltage (de, , di) C 0.5 v to + 4 v receiver input (a, b) voltage half - duplex ( adn4690e , ADN4694E ) C 1.8 v to + 4 v full - duplex ( adn4692e , adn4695e ) C 4 v to + 6 v receiver output voltage (ro) C 0.3 v to + 4 v driver output (a, b, y, z) voltage C 1.8 v to + 4 v esd rating (a, b, y, z pins) hbm (human body model) air d ischarge 15 kv contact d ischarge 8 kv iec 61000 - 4 - 2, air d ischarge 10 kv iec 61000 -4- 2, contact d ischarge 8 kv esd rating (other pins, hbm) 4 kv esd rating (a ll pins) ficdm 1.25 kv machine model 400 v operating temperature range ?40c to +85c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 7 . thermal resistance package type ja unit 8- lead soic 121 c/w 14 - lead soic 86 c/w esd caution
data sheet adn4690e/adn4692e/ADN4694E/adn4695e rev. a | page 7 of 20 pin configuration s and function descrip tions ro 1 re 2 de 3 di 4 v cc 8 b 7 a 6 gnd 5 adn4690e/ ADN4694E t op view (not to scale) 10471-002 figure 3 . adn4690e / ADN4694E pin configuration nc 1 2 3 4 v cc 14 13 12 1 1 5 10 gnd 6 y 9 gnd 7 nc 8 notes 1. nc = no connec t . do not connect t o this pin. adn4692e/ adn4695e t op view (not to scale) ro re de di v cc a b z 10471-104 figure 4 . adn4692e / adn4695e pin configuration table 8 . pin function descriptions adn4690e / ADN4694E pin no. adn4692e / adn4695e pin no. mnemonic description 1 2 ro receiver output. type 1 receiver ( a dn4690e / adn4692e ) , when enabled: i f a ? b 50 mv, then ro = logic high. if a ? b ?50 mv, then ro = logic low. type 2 receiver ( ADN4694E / adn4695e ), when enabled: i f a ? b 15 0 mv, then ro = l ogic high. if a ? b 5 0 mv, then ro = logic low . receiver o utput is undefined outside the se conditions . 2 3 re receiver output enable. a logic low on this pin enables the receiver output, ro. a logic high on this pin places ro in a high impedance state. 3 4 de driver output enable. a logic high on this pin enables the driver differential output s . a logic low on this pin places the driver differential outputs in a high impedance state. 4 5 di driver input. half - d uplex ( adn4690e / ADN4694E ), when enabled: a logic low on di forces a low and b high, whereas a logic high on di forces a high and b low. full - d uplex ( adn4692e / adn4695e ), when enabled: a logic lo w on di forces y low and z high, whereas a logic high on di forces y high and z low. 5 6, 7 gnd ground. n/a 9 y non inverting driver output y . n/a 10 z inverting driver output z. 6 n/a a non inv erting receiver input a and non inverting driver output a. n/a 12 a non inverting receiver input a. 7 n/a b inverting receiver input b and inverting driver output b. n/a 11 b inverting receiver input b. 8 13, 14 v cc power supply (3.3 v 0.3 v). n/a 1, 8 nc no connect. do not connect to these pin s .
adn4690e/adn4692e/ADN4694E/adn4695e data sheet rev. a | page 8 of 20 typical performance characteristics 0 6 4 2 8 10 12 14 16 18 20 10 15 20 25 30 35 40 45 50 supp l y curren t , i cc (ma) frequenc y (mhz) 10471-003 driver receiver (v id = 200m v , v ic = 1v) figure 5 . power supply current vs. frequency (v cc = 3.3 v, t a = 25c ) 0 5 10 15 20 25 30 ?40 ?20 0 20 40 60 80 supp l y curren t , i cc (ma) temper a ture (c) 10471-004 driver receiver (v id = 200m v , v ic = 1v) figure 6 . power supply current vs. temperature ( data rate = 1 00 m bps , v cc = 3.3 v ) 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5 4 . 0 r ec ei ver l ow l eve l o u t pu t curr en t , i o l (m a ) r ec ei ver l o w l eve l o u t pu t vo l t a g e, v o l (v) v c c = 3 v v c c = 3 . 3 v v c c = 3 . 6 v 10471 - 005 figure 7 . receiver output current vs. output voltage (output low) ( t a = 25c) ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 receiver high leve l output current (ma) receiver high leve l output vo lt age, v oh (v) v cc = 3.0v v cc = 3. 3 v v cc = 3. 6 v 10471-006 figure 8 . receiver output current vs. output voltage (output high) ( t a = 25c) 2.0 2.2 2.4 2.6 3.0 2.8 3.2 3.4 ?40 ?20 0 20 40 60 80 driver pro p ag a tion del a y (ns) temper a ture (c) 10471-007 t plh t ph l figure 9 . driver propagation delay vs. temperature (data rate = 2 mbps, v cc = 3.3 v , r l = 50 ? ) 2.0 2.5 3.0 3.5 4.0 5.0 4.5 5.5 6.0 ?40 ?20 0 20 40 60 80 receiver pro p ag a tion del a y (ns) temper a ture (c) 10471-008 t rplh t rph l figure 10 . receiver propagation delay vs. tempe rature (data rate = 2 mbps, v cc = 3.3 v , v id = 200 mv, v ic = 1 v, c l = 15 pf )
data sheet adn4690e/adn4692e/ADN4694E/adn4695e rev. a | page 9 of 20 0 1.0 0.5 1.5 2.0 2.5 3.0 20 40 60 80 100 added driver period jitter (ps) frequenc y (mhz) 10471-009 figure 11 . driver jitter (period) vs. frequency (v cc = 3.3 v, t a = 25c, clock input) 0 6 4 2 8 10 12 14 16 18 20 20 30 40 50 60 70 80 90 100 added driver peak- t o-peak jitter (ps) dat a r a te (mbps) 10471-010 figure 12 . driver jitter (peak - to - peak) vs. data rate (v cc = 3.3 v, t a = 25c, prbs 2 15 ? 1 nrz input ) 0 10 20 30 40 50 60 80 70 90 100 ?40 ?20 0 20 40 60 80 added driver peak- t o-peak jitter (ps) temper a ture (c) 10471-0 1 1 figure 13 . driver jitter (peak - to - peak) vs. temperature (data rate = 1 00 mbps, v cc = 3.3 v, t a = 25c, prbs 2 15 ? 1 nrz input) 0 3 2 1 4 5 6 7 10 20 30 40 50 added receiver period jitter (ps) frequenc y (mhz) 10471-012 figure 14 . receiver jitter (period) vs. frequency (v cc = 3.3 v, t a = 25c, v ic = 1 v, clock input) 0 100 200 300 500 400 600 700 ?40 ?20 0 20 40 60 80 added receiver peak- t o-peak jitter (ps) temper a ture (c) 10471-014 figure 15 . receiver jitter (peak - to - peak) vs. temperature (v cc = 3.3 v , v i c = 1 v , prbs 2 15 ? 1 nrz input )
adn4690e/adn4692e/ADN4694E/adn4695e data sheet rev. a | page 10 of 20 10471-015 2ns/div 200mv/div figure 16 . adn4690e driver output eye pattern (data rate = 100 mbps , prbs 2 15 ? 1 input , r l = 50 ? ) 10471-016 2.5ns/div 400mv/div figure 17 . adn4690e receiver output eye pattern (data rate = 100 mbps , prbs 2 15 ? 1 , c l = 15 pf )
data sheet adn4690e/adn4692e/ADN4694E/adn4695e rev. a | page 11 of 20 test circuits and switching charac teristics driver voltage and c urrent measurements di notes 1. 1% t olerance for al l resis t ors. v od v test 49.9? 3.32k? + ? 3.32k? 10471-017 a/ y b/z v test = ?1v t o +3.4v figure 18 . driver voltage measurement over common - mode range di notes 1. c1, c2, and c3 are 20% and include probe/str a y ca p aci t ance < 2cm from du t . 2. r1 and r2 are 1%, me t al film, sur f ace moun t , <2cm from du t . v oc r1 24.9? c1 1pf c2 1pf c3 2.5pf r2 24.9? 10471-018 a/ y b/z figure 19 . driver common - mode output voltage measurement s1 s2 v a(o) , v b(o) , v y(o) or v z(o) a/ y v cc r1 1.62k? 1% b/z de 10471-019 figure 20 . maximum steady - state output voltage measurement s1 di s2 v test v cc i os v test = ?1v or +3.4v 10471-020 a/ y b/z figure 21 . driver short circuit notes 1. input pulse gener a t or: 1mhz; 50% 5% dut y cycle; t r , t f 1ns. 2. v oc(pp) measured on test equipment with C3db bandwidth 1ghz. v oc(pp) v oc(ss) v oc b a 0.7v 1.3v 10471-021 figure 22 . driver common - mode output voltage ( steady state)
adn4690e/adn4692e/ADN4694E/adn4695e data sheet rev. a | page 12 of 20 driver timing measur ements di notes 1. c1, c2, and c3 are 20% and include probe/str a y ca p aci t ance < 2cm from du t . 2. r1 is 1%, me t al film, sur f ace moun t , <2cm from du t . out c1 1pf c3 0.5pf c2 1pf 10471-022 r1 50? a/ y b/z figure 23 . driver timing measurement di de s1 v cc notes 1. c1, c2, c3, and c4 are 20% and include probe/stray capacitance < 2cm from dut. 2. r1 and r2 are 1%, metal film, surface mount, <2cm from dut. r1 24.9? c1 1pf c2 1pf c3 2.5pf r2 24.9? 10471-023 c4 0.5pf out a/y b/z figure 24 . driver enable/disable time test circuit notes 1. input pulse gener a t or: agilent 8304 a stimulus system; 50mhz; 50% 1% dut y cycle. 2. measured using tek tds6604 with tdsjit3 soft w are. v cc /2 v cc /2 v cc 0v 1/f0 input (clock) 10471-024 0v 0v 1/f0 output v a ? v b or v y ? v z (ideal) 0v 0v t c(n) t j(per) = | t c(n) ? 1/f0| output v a ? v b or v y ? v z (actual) figure 25 . driver period jitter c haracteristics notes 1. input pulse gener a t or: 1mhz; 50% 5% dut y cycle; t r , t f 1ns. 2. measured on test equipment with C3db bandwidth 1ghz. t plh t r t f t ph l v cc v ss v ph v pl 0% v ss 10% v ss 90% v ss 0v 0v 0v out di 10471-025 10% v ss 90% v ss v cc /2 v cc /2 figure 26 . driver propagation, rise/fall times and voltage overshoot 0.5v cc 0.5v cc v cc 0v 0v 0v ~ ?0.6v ~ +0.6v ?0.1v 0.1v 0.1v de out (di = 0v) out (di = v cc ) 10471-026 t pzh t pz l ?0.1v t phz t plz notes 1. input pulse gener a t or: 1mhz; 50% 5% dut y cycle; t r , t f 1ns. 2. measured on test equipment with C3db bandwidth 1ghz. figure 27 . driver enable/disable times notes 1. input pulse gener a t or: agilent 8304 a stimulus system; 100mbps; 2 15 ? 1prbs. 2. measured using tek tds6604 with tdsjit3 soft w are. v a ? v b or v y ? v z v a ? v b or v y ? v z v cc output input (prbs) 0v v cc /2 t j(pp) 0v 0v v cc /2 10471-027 figure 28 . driver peak - to - peak jitter characte ristics
data sheet adn4690e/adn4692e/ADN4694E/adn4695e rev. a | page 13 of 20 receiver timing measurements a notes 1. c l is 20%, ceramic, surface mount, and includes probe/stray capacitance < 2cm from dut. v out c l 15pf b 10471-028 ro re v id figure 29 . receiver timing measurement a 1.4v 1.0v s1 1.2v re input notes 1. c l is 20% and includes probe/stray capacitance < 2cm from dut. 2. r l is 1% metal film, surface mount, <2cm from dut. v out c l 15pf r l 499? b 10471-029 ro re v test figure 30 . receiver enable/disable time notes 1. input pulse gener a t or: agilent 8304 a stimulus system; 50mhz; 50% 1% dut y cycle. 2. measured using tek tds6604 with tdsjit3 soft w are. v oh v ol 1/f0 input (v a ? v b ) 10471-030 0.5v cc 0.5v cc 0.5v cc 0.5v cc 1/f0 output (ideal) v oh v ol output (actual) t c(n) t j(per) = | t c(n) ? 1/f0| figure 31 . receiver period jitter characteristi cs notes 1. input pulse gener a t or: 1mhz; 50% 5% dut y cycle; t r , t f 1ns. 2. measured on test equipment with C3db bandwidth 1ghz. v cc /2 v cc /2 v oh v id v b v a v ol v out 90% 0v 0v 10% 90% 10% t f t r t rplh t rph l 10471-031 figure 32 . receiver propagation and rise/fall times 0.5v cc 0.5v cc v cc 0v v cc 0v v ol v oh 0.5v cc 0.5v cc v oh ? 0.5v re input (v test = v cc ) (a = 1v) v out v out (v test = 0v) (a = 1.4v) 10471-032 t rpzh t rpz l v ol + 0.5v t rphz t rplz notes 1. input pulse gener a t or: 1mhz; 50 5% dut y cycle; t r , t f 1ns. figure 33 . receiver enable/disable times notes 1. input pulse gener a t or: agilent 8304 a stimulus system; 100mbps; 2 15 ? 1prbs. 2. measured using tek tds6604 with tdsjit3 soft w are. v oh v ol v a v b output input (prbs) t j(pp) v cc /2 v cc /2 10471-033 figure 34 . receiver peak - to - peak jitter characteristics
adn4690e/adn4692e/ADN4694E/adn4695e data sheet rev. a | page 14 of 20 theory of ope ration the adn4690e / adn4692e / ADN4694E / adn4695e are transceivers for transmitting and receiving multipoint, low voltage differential signaling (m - lvds) at high speed (data rates up to 100 mbps). each device has a differential line driver and a differential line receiver, allowing each device to send and receive data. m ultipoint lvds expands on the established lvds low voltage differential signa ling method by allowing bidirectional commu - nication between more than two nodes. up to 32 nodes can be connected on an m - lvds bus. half - duplex /full - duplex operation half - duplex o peration allows a transceiver to transmit or receive, but not both at the same time . however, with full - duplex operation, a transceiver can transmit and receive simultaneously. the adn4690e / ADN4694E are half - duplex device s in which the driver and the receiver share differential bus terminals. the adn4692e / adn4695e are full - duplex device s that ha ve dedicated driver output and receiver input pins. figure 36 and figure 37 show typical half - and full - duplex bus topologies , respectively, for m - lvds . three -s tate bus connecti on the outputs of the device can be placed in a high impedance state by disabling the driver or receiver. this allows several driver outputs to be connected to a single m - lvds bus. note that , on each bus line , only one driver can be enabled at a time, but many receivers can be enabled at the same time . the driver can be enabled or disabled using the driver enable pin (de) . de enables the driver outputs when taken high; when taken low, de puts the driver outputs into a high impedance state. similarly, an act ive low receiver enable pin ( re ) controls the receiver . taking this pin low enables the receiver, whereas taking it high puts the receiver outputs into a high impedance state. truth tables for driver and receiver output states under vario us conditions are shown in table 10 , table 11, table 12, and table 13. truth tables table 9 . truth table abbreviations abbreviat ion description h high level l low level x dont care i indeterminate z high impedance (off ) nc disconnected driver, half duplex ( adn4690e / ADN4694E ) ta ble 10 . transmitting (see table 9 for abbreviations) power inputs outputs de di a b yes h h h l yes h l l h yes h nc l h yes l x z z yes nc x z z 1.5 v x x z z driver, full duplex ( adn4692e / adn4695e ) table 11 . transmitting (see table 9 for abbreviations) power inputs outputs de di y z yes h h h l yes h l l h yes h nc l h yes l x z z yes nc x z z 1.5 v x x z z type 1 receiver ( adn4690e / adn4692e ) table 12 . receiving (see table 9 for abbreviations) power inputs output a ? b re r o yes 50 m v l h yes ? 50 m v l l yes ? 50 mv < a ? b < 50 m v l i yes nc l i yes x h z yes x nc z no x x z type 2 receiver ( ADN4694E / adn4695e ) table 13 . receiving (see table 9 for abbreviations) power inputs output a ? b re r o yes 150 m v l h yes 50 m v l l yes 50 m v < a ? b < 150 m v l i yes nc l l yes x h z yes x nc z no x x z
data sheet adn4690e/adn4692e/ADN4694E/adn4695e rev. a | page 15 of 20 glitch - free power - up/power - down to minimize disruption to the bus when adding nodes, the m - lvds outputs of the device are kept glitch - free when the device is powering up or down. this feature allows insertion of d evices onto a live m - lvds bus because the bus outputs are not switched on before the device is fully powered. in addition, all outputs are placed in a high impedance state when the device is powered off. fault conditions the adn4690e / adn4692e / ADN4694E / adn4695e contain short - circuit current protection that protect s the part under fault conditions in the case of short circuits on the bus. this protection limit s the current in a fault condition to 24 ma at the transmitter outputs for short - circuit faults between ? 1 v and +3.4 v. any network fault must be cleared to avoid data transmission errors and to ensure reliable operation of the data network and any devices that are connected to the network. receiver input thres holds/fail -s afe two receiver types are availabl e, both of which incor porate protection against short circuits. the type 1 receivers of the adn4690e / adn4692e incorporate 25 mv of hysteresis. this ensures that slow - changing signals or a loss of input does not result in oscillation of the receiver output. type 1 receiver thresholds are 50 mv; therefore, the state of the receiver output is indeterminate if the differential between a and b is about 0 v. this stat e occurs if the bus is idle (approximately 0 v on both a and b), with no drivers enabled on the attached nodes. type 2 receivers ( ADN4694E / adn4695e ) have an op en circuit and bus - idle fail - safe. the input threshold is offset by 100 mv so that a logic low is present on the receiver output when the bus is idle or when the receiver inputs are open. the different receiver thresholds for the two receiver types are ill ustrated in figure 35. see table 12 and table 13 for receiver output states under various conditions. type 1 receiver output logic 1 logic 0 differentia l input vo lt age (v ia ? v ib ) [v] 0.25 0.15 0.05 ?0.05 ?0.15 0 10471-034 undefined type 2 receiver output logic 1 logic 0 undefined figure 35 . input threshold voltages
adn4690e/adn4692e/ADN4694E/adn4695e data sheet rev. a | page 16 of 20 applicatio ns information m - lvds extends the low power, high speed, differential signal - ing of lvds ( low voltage differential signal ing) to multipoint systems where multiple nodes are connected over short distances in a bus topology network. with m - lvds, a transmitt ing node drives a differential signal across a transmission medium such as a twisted pair cable. the transmitted differential signal allows other receiving nodes that are connected along the bus to detect a diffe rential voltage that can then be converted b ack into a single - ended logic signal by the receiver. the communication line is typic ally terminated at both ends by resistors ( r t ), the value of which is chosen to match the characteristic impedance of the medium (typically 100 ?). for half - duplex multi point applications such as the one shown in figure 36 , only one driver c an be enabled at any time. full - dupl ex nodes allow a master slave topology , as shown in figure 37 . in this configuration, a master node can concurrently send and receive data to/from slave nodes. at any time, only one slave node can have its driver enabled to concur rently transmit data back to the master node. ro notes 1. maximum number of nodes: 32. 2. r t is equa l t o the characteristic impedance of the cable used. re a b r t r t ADN4694E de di ro re a b ADN4694E de di ro re a b ADN4694E de di ro re a b ADN4694E de di 10471-035 figure 36 . ADN4694E typical half - duplex m - lvds network (type 2 receivers with thr eshold offset for bus - idle fail - safe) ro notes 1. maximum number of nodes: 32. 2. r t is equa l t o the characteristic impedance of the cable used. re a b z y master sla ve sla ve sla ve r t r t adn4695e de di ro re de di ro re de di a b z y adn4695e a b z y adn4695e a b z y adn4695e r t r t ro re de di 10471-036 r d r d r d r d figure 37 . adn4695e typical full - duplex m - lvds master - slave network (type 2 receivers with thr eshold offset for bus - idle fail - safe)
data sheet adn4690e/adn4692e/ADN4694E/adn4695e rev. a | page 17 of 20 outline dimensions controlling dimensions are in millimeters; inch dimensions (in p arentheses) are rounded-off millimeter equiv alents for reference onl y and are not appropria te for use in design. compliant t o jedec st andards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) sea ting plane 0.25 (0.0098) 0.10 (0.0040) 4 1 8 5 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 38 . 8 - le ad standard small outline package [soic_n] narrow body (r - 8) dimensions shown in millimeters and (inches) controlling dimensions are in millimeters; inch dimensions (in p arentheses) are rounded-off millimeter equi v alents for reference on l y and are not appropri a te for use in design. compliant t o jedec s t andards ms-012-ab 060606- a 14 8 7 1 6.20 (0.2441) 5.80 (0.2283) 4.00 (0.1575) 3.80 (0.1496) 8.75 (0.3445) 8.55 (0.3366) 1.27 (0.0500) bsc sea ting plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) coplanarit y 0.10 8 0 45 figure 39 . 14- lead standard small outline package [soic_n] narrow body (r - 14) dimensions shown in millimeters and (inches) ordering guide model 1 temperature range package description package option adn4690e brz C 40c to +85c 8- lead standard small outline package (soic_n) r -8 adn4690e brz - rl7 C 40c to +85c 8- lead standard small outline package (soic_n) r -8 adn4692e brz C 40c to +85c 14- lead standard small outline package (soic_n) r -14 adn4692e brz - rl7 C 40c to +85c 14- lead standard small outline package (soic_n) r -14 ADN4694Ebrz C 40c to +85c 8- lead standard small outline package (soic_n) r -8 ADN4694Ebrz - rl7 C 40c to +85c 8- lead standard small outline package (soic_n) r -8 adn4695ebrz C 40c to +85c 14- lead standard small outline package (soic_n) r -14 adn4695ebrz - rl7 C 40c to +85c 14- lead standard small outline package (soic_n) r -14 eval - adn469xehdebz evaluation boar d for half - duplex m - lvds (adn4690e, ADN4694E) eval - adn469xefdebz evaluation board for full - duplex m - lvds (adn4692e, adn4695e) 1 z = rohs compliant part.
adn4690e/adn4692e/ADN4694E/adn4695e data sheet rev. a | page 18 of 20 notes
data sheet adn4690e/adn4692e/ADN4694E/adn4695e rev. a | page 19 of 20 notes
adn4690e/adn4692e/ADN4694E/adn4695e data sheet rev. a | page 20 of 20 notes ?2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d10471-0-3/12(a)

▲Up To Search▲

Price & Availability of ADN4694E

	To Download ADN4694E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .